Staff DFT Engineer

Campbell, California

Start 12/06/2021

Permanent

We are seeking a seasoned DFT Engineer with a minimum of 15+ years of experience to join our ASIC team. Candidates should have prior experience defining the DFT Architecture and executing on the DFT implementation plan. This means defining the methodology, setting up the environment and driving the Synthesis/Formal

We are seeking a seasoned DFT Engineer with a minimum of 15+ years of experience to join our ASIC team. Candidates should have prior experience defining the DFT Architecture and executing on the DFT implementation plan. This means defining the methodology, setting up the environment and driving the Synthesis/Formal Implementation flows in a Hierarchical DFT environment. Comprehensive understanding of the issues faced between the RTL, DFT, and Physical design teams. Good understanding of clocking structures and tradeoffs between power, area, and timing.

QUALIFICATIONS:

  • Expertise in SDC(synthesis design constraints) and Verilog is mandatory
  • Experience leading ASIC infrastructure, defining methodology, and driving the DFT flows
  • Expertise in ACJTAG/BSD/1500 wrappers
  • Expertise in Scan/On chip Clocking/@speed Test (TDF) /Path Delay
  • Prior experience with Serializers and in system scan
  • Strong experience in ECO methodology
  • Experience driving Backend test generation and wafer/ATE Test with external vendors
  • Prior experience working with hardware team to promote SDC’s in a multi-level Physical hierarchical design(Hierarchical DFT/Test)
  • Experience working with Physical Design and Timing teams to refine constraints

REQUIREMENTS:
  • Work with Timing team to consolidate Timing Modes, STA experience preferred
  • PERL /TCL programming ability required
  • Prior tape out experience required in a 16nm or smaller node
  • Strong communication and presentation skills.
  • BSEE/MSEE is required.