Physical Design Engineer

Campbell, California

Start 12/06/2021

Permanent

Our client is seeking a seasoned  “Hands-on” Physical Design Engineer with a minimum of 10+ years of experience to join our ASIC team. Person should have prior in defining the Physical Architecture and executing on the implementation plan. This means defining the methodology, setting up the
Our client is seeking a seasoned  “Hands-on” Physical Design Engineer with a minimum of 10+ years of experience to join our ASIC team. Person should have prior in defining the Physical Architecture and executing on the implementation plan. This means defining the methodology, setting up the environment and driving the Floor Planning, including the DFT architecture. Comprehensive understanding of the issues faced between the RTL, DFT and the Physical design teams. Good understanding of clocking structures and tradeoffs between power, area, and timing.


QUALIFICATIONS:

  • Expertise in SDC(synthesis design constraints) is mandatory
  • Experience leading ASIC infrastructure, defining methodology, and driving the DFT/PD flows
  • Strong experience in Clock Architecture particularly with multiple PLLs/DLLs – and various clock tree Architectures including H Tree/ Clock Mesh
  • Ability to manage and drive External PD resources to a successful implementation of a large Hierarchical SOC
  • Experience working with Physical design, RTL, and timing teams to refine constraints.
  • Experience working with Timing team to consolidate Timing Modes. Some STA experience is preferred

REQUIREMENTS:
  • PERL /TCL/Python programming ability required
  • Prior tape out experience required in a 16nm or smaller node
  • Strong experience in either Cadence or Synopsys tool environments
  • Strong communication and presentation skills.
  • BSEE/MSEE is required.